FAQs
What is the job title for the position being offered?
The job title is Principal Digital Verification Engineer.
What is the main location for this job?
The main location for this job is Cork.
Who does the Principal Digital Verification Engineer report to?
The Principal Digital Verification Engineer reports to the Design Engineering Director.
What are the primary responsibilities of this position?
The primary responsibilities include architecture of verification environments, leading development of Formal First methodologies, collaboration with design engineers, development of SystemVerilog assertions, and various other verification tasks.
What qualifications are required for this role?
A degree in Electrical/Electronic Engineering or a related discipline, along with 10+ years of experience in the microelectronics/EDA industry, is required.
Is experience in Verilog RTL Design essential for this position?
Yes, experience in Verilog RTL Design is essential for this position.
Are there any preferred additional skills for this job?
Yes, experience in quality processes like ISO-9001 & ISO-26262 and AMBA protocols such as AXI, AHB & APB is preferred.
Will there be opportunities for technical leadership in this role?
Yes, having experience in technical team leadership is considered an advantage for this role.
What is the travel requirement for this position?
The travel requirement for this position is less than 5%.
Does Cadence support diversity and inclusion in the workplace?
Yes, Cadence is committed to equal employment opportunity and encourages diversity and inclusion throughout all levels of the organization.
